MIT Technology Review is reporting that IBM has developed a new prototype chip containing approximately 100 billion transistors, achieving twice the density of its prior state-of-the-art technology from 2021. The publication said this design could lead to faster and more energy-efficient computers for years to come.
The new architecture, called a nanostack, vertically stacks transistors in two layers on a silicon chip. IBM Research director Jay Gambetta described it as a "meaningful leap forward," moving beyond the traditional shrinking of transistors to overcome the physical limits of Moore's Law. The company reports that chips built with this approach can perform up to 50% more work in the same timeframe and be up to 70% more energy efficient compared to IBM's previous architecture.
MIT Technology Review said industry experts, such as Dan Hutcheson, vice chair of TechInsights, consider the development "transformational," potentially extending the chip roadmap by 10 to 15 years. Gambetta anticipates nanostacking chips will be widely adopted in data centers within a decade, improving energy management.
The design employs a complementary field-effect transistor, or CFET, approach, which involves fabricating transistors layer by layer. While other major chip manufacturers like Intel, Samsung and TSMC are also exploring CFETs, IBM's design distinguishes itself by staggering the second layer of transistors, which it says simplifies wiring. IBM plans to partner with semiconductor manufacturers to produce the actual chips, expecting the design to be used in various chip types, including GPUs and CPUs.
The publication noted that manufacturing challenges for multi-tiered chips include higher failure rates and managing the "thermal budget" to prevent melting connections during fabrication. IBM stated it has addressed the temperature challenge for its two-layer stack.
Full Article: IBM has unveiled chip technology that could help extend Moore’s Law another decade